Model {
  Name			  "automat_konz_speicher2"
  Version		  6.0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.43"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "ibm-5348_P100-1997"
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Mon Oct 18 11:38:40 2004"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "Florian Knorn"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Mon Oct 18 13:56:58 2004"
  ModelVersionFormat	  "1.%<AutoIncrement:43>"
  ConfigurationManager	  "None"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  ProdHWDeviceType	  "32-bit Generic"
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
    Simulink.ConfigSet {
      $ObjectID		      1
      Version		      "1.0.4"
      Array {
	Type			"Handle"
	Dimension		7
	Simulink.SolverCC {
	  $ObjectID		  2
	  Version		  "1.0.4"
	  StartTime		  "0.0"
	  StopTime		  "1e6"
	  AbsTol		  "auto"
	  FixedStep		  "1"
	  InitialStep		  "auto"
	  MaxNumMinSteps	  "-1"
	  MaxOrder		  5
	  ExtrapolationOrder	  4
	  NumberNewtonIterations  1
	  MaxStep		  "auto"
	  MinStep		  "auto"
	  RelTol		  "1e-3"
	  SolverMode		  "Auto"
	  Solver		  "FixedStepDiscrete"
	  ZeroCrossControl	  "UseLocalSettings"
	  PositivePriorityOrder	  off
	  AutoInsertRateTranBlk	  off
	  SampleTimeConstraint	  "Unconstrained"
	  RateTranMode		  "Deterministic"
	}
	Simulink.DataIOCC {
	  $ObjectID		  3
	  Version		  "1.0.4"
	  Decimation		  "1"
	  ExternalInput		  "[t, u]"
	  FinalStateName	  "xFinal"
	  InitialState		  "xInitial"
	  LimitDataPoints	  on
	  MaxDataPoints		  "1000"
	  LoadExternalInput	  off
	  LoadInitialState	  off
	  SaveFinalState	  off
	  SaveFormat		  "Array"
	  SaveOutput		  on
	  SaveState		  off
	  SaveTime		  on
	  StateSaveName		  "xout"
	  TimeSaveName		  "tout"
	  OutputSaveName	  "yout"
	  SignalLoggingName	  "logsout"
	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
	  Refine		  "1"
	}
	Simulink.OptimizationCC {
	  $ObjectID		  4
	  Array {
	    Type		    "Cell"
	    Dimension		    5
	    Cell		    "ZeroExternalMemoryAtStartup"
	    Cell		    "ZeroInternalMemoryAtStartup"
	    Cell		    "InitFltsAndDblsToZero"
	    Cell		    "OptimizeModelRefInitCode"
	    Cell		    "NoFixptDivByZeroProtection"
	    PropName		    "DisabledProps"
	  }
	  Version		  "1.0.4"
	  BlockReduction	  on
	  BooleanDataType	  on
	  ConditionallyExecuteInputs on
	  ConditionalExecOptimization "on_for_testing"
	  InlineParams		  off
	  InlineInvariantSignals  on
	  OptimizeBlockIOStorage  on
	  BufferReuse		  on
	  EnforceIntegerDowncast  on
	  ExpressionFolding	  on
	  FoldNonRolledExpr	  on
	  LocalBlockOutputs	  on
	  ParameterPooling	  on
	  RollThreshold		  5
	  SystemCodeInlineAuto	  off
	  StateBitsets		  off
	  DataBitsets		  off
	  UseTempVars		  off
	  ZeroExternalMemoryAtStartup on
	  ZeroInternalMemoryAtStartup on
	  InitFltsAndDblsToZero	  on
	  NoFixptDivByZeroProtection off
	  OptimizeModelRefInitCode off
	  LifeSpan		  "inf"
	}
	Simulink.DebuggingCC {
	  $ObjectID		  5
	  Version		  "1.0.4"
	  ConsistencyChecking	  "none"
	  ArrayBoundsChecking	  "none"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  CheckSSInitialOutputMsg on
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "TryResolveAllWithWarning"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  SolverPrmCheckMsg	  "warning"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterPrecisionLossMsg "warning"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  UniqueDataStoreMsg	  "none"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  ModelReferenceSimTargetVerbose off
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	}
	Simulink.HardwareCC {
	  $ObjectID		  6
	  Version		  "1.0.4"
	  ProdBitPerChar	  8
	  ProdBitPerShort	  16
	  ProdBitPerInt		  32
	  ProdBitPerLong	  32
	  ProdIntDivRoundTo	  "Undefined"
	  ProdEndianess		  "Unspecified"
	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
	  ProdHWDeviceType	  "32-bit Generic"
	  TargetBitPerChar	  8
	  TargetBitPerShort	  16
	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
	  TargetEndianess	  "Unspecified"
	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
	  ProdEqTarget		  on
	}
	Simulink.ModelReferenceCC {
	  $ObjectID		  7
	  Version		  "1.0.4"
	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  ModelReferenceNumInstancesAllowed "Multi"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
	}
	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
	  $ObjectID		  8
	  Array {
	    Type		    "Cell"
	    Dimension		    1
	    Cell		    "IncludeHyperlinkInReport"
	    PropName		    "DisabledProps"
	  }
	  Version		  "1.0.4"
	  SystemTargetFile	  "grt.tlc"
	  GenCodeOnly		  off
	  MakeCommand		  "make_rtw"
	  TemplateMakefile	  "grt_default_tmf"
	  GenerateReport	  off
	  SaveLog		  off
	  RTWVerbose		  on
	  RetainRTWFile		  off
	  ProfileTLC		  off
	  TLCDebug		  off
	  TLCCoverage		  off
	  TLCAssert		  off
	  ProcessScriptMode	  "Default"
	  ConfigurationMode	  "Optimized"
	  ConfigAtBuild		  off
	  IncludeHyperlinkInReport off
	  LaunchReport		  off
	  Array {
	    Type		    "Handle"
	    Dimension		    2
	    Simulink.CodeAppCC {
	      $ObjectID		      9
	      Array {
		Type			"Cell"
		Dimension		9
		Cell			"IgnoreCustomStorageClasses"
		Cell			"InsertBlockDesc"
		Cell			"SFDataObjDesc"
		Cell			"SimulinkDataObjDesc"
		Cell			"DefineNamingRule"
		Cell			"SignalNamingRule"
		Cell			"ParamNamingRule"
		Cell			"InlinedPrmAccess"
		Cell			"CustomSymbolStr"
		PropName		"DisabledProps"
	      }
	      Version		      "1.0.4"
	      ForceParamTrailComments off
	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
	      IncHierarchyInIds	      off
	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
	      ShowEliminatedStatement off
	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
	      IncDataTypeInIds	      off
	      PrefixModelToSubsysFcnNames on
	      CustomSymbolStr	      "$R$N$M"
	      MangleLength	      1
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		12
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      Version		      "1.0.4"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Courier New"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Constant
      Value		      "1"
      VectorParams1D	      on
      OutDataTypeMode	      "Inherit from 'Constant value'"
      OutDataType	      "sfix(16)"
      ConRadixGroup	      "Use specified scaling"
      OutScaling	      "2^0"
      SampleTime	      "inf"
    }
    Block {
      BlockType		      Display
      Format		      "short"
      Decimation	      "10"
      Floating		      off
      SampleTime	      "-1"
    }
    Block {
      BlockType		      SignalConversion
      OverrideOpt	      off
    }
    Block {
      BlockType		      Inport
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Configuration Parameters: Optimiza"
"tion)"
      LogicDataType	      "uint(8)"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Memory
      X0		      "0"
      InheritSampleTime	      off
      LinearizeMemory	      off
      StateMustResolveToSignalObject off
      RTWStateStorageClass    "Auto"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Switch
      Criteria		      "u2 >= Threshold"
      Threshold		      "0"
      InputSameDT	      on
      OutDataTypeMode	      "Inherit via internal rule"
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      ZeroCross		      on
      SampleTime	      "-1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Courier New"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Courier New"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "automat_konz_speicher2"
    Location		    [2, 98, 1278, 1003]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      SubSystem
      Name		      "AND\n6_1"
      Ports		      [8, 4]
      Position		      [485, 271, 535, 449]
      BackgroundColor	      "magenta"
      FontSize		      18
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "fprintf('4x\\n\\nAND')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      Port {
	PortNumber		1
	Name			"  __\nx.z1"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		2
	Name			"_ __\nx.z0"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		3
	Name			"_   \nx.z0"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		4
	Name			"x.z1"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"AND\n6_1"
	Location		[471, 411, 811, 724]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 28, 55, 42]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 43, 55, 57]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In3"
	  Position		  [25, 98, 55, 112]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In4"
	  Position		  [25, 113, 55, 127]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In5"
	  Position		  [25, 168, 55, 182]
	  Port			  "5"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In6"
	  Position		  [25, 183, 55, 197]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In7"
	  Position		  [25, 238, 55, 252]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In8"
	  Position		  [25, 253, 55, 267]
	  Port			  "8"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator3"
	  Ports			  [2, 1]
	  Position		  [80, 27, 110, 58]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator4"
	  Ports			  [2, 1]
	  Position		  [80, 97, 110, 128]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator5"
	  Ports			  [2, 1]
	  Position		  [80, 167, 110, 198]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator6"
	  Ports			  [2, 1]
	  Position		  [80, 237, 110, 268]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [135, 38, 165, 52]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out2"
	  Position		  [135, 108, 165, 122]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out3"
	  Position		  [135, 178, 165, 192]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out4"
	  Position		  [135, 248, 165, 262]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator3"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In3"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator4"
	  SrcPort		  1
	  DstBlock		  "Out2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In4"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In5"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator5"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator5"
	  SrcPort		  1
	  DstBlock		  "Out3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In6"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In7"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator6"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator6"
	  SrcPort		  1
	  DstBlock		  "Out4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In8"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator6"
	  DstPort		  2
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "AND\n6_2"
      Ports		      [8, 4]
      Position		      [935, 259, 985, 441]
      BackgroundColor	      "magenta"
      FontSize		      18
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "fprintf('4x\\n\\nAND')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      Port {
	PortNumber		1
	Name			"y1"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		4
	Name			"y0"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"AND\n6_2"
	Location		[572, 200, 762, 494]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 28, 55, 42]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 43, 55, 57]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In3"
	  Position		  [25, 98, 55, 112]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In4"
	  Position		  [25, 113, 55, 127]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In5"
	  Position		  [25, 168, 55, 182]
	  Port			  "5"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In6"
	  Position		  [25, 183, 55, 197]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In7"
	  Position		  [25, 238, 55, 252]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In8"
	  Position		  [25, 253, 55, 267]
	  Port			  "8"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator3"
	  Ports			  [2, 1]
	  Position		  [80, 27, 110, 58]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator4"
	  Ports			  [2, 1]
	  Position		  [80, 97, 110, 128]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator5"
	  Ports			  [2, 1]
	  Position		  [80, 167, 110, 198]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator6"
	  Ports			  [2, 1]
	  Position		  [80, 237, 110, 268]
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [135, 38, 165, 52]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out2"
	  Position		  [135, 108, 165, 122]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out3"
	  Position		  [135, 178, 165, 192]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out4"
	  Position		  [135, 248, 165, 262]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator3"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In3"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator4"
	  SrcPort		  1
	  DstBlock		  "Out2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In4"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In5"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator5"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator5"
	  SrcPort		  1
	  DstBlock		  "Out3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In6"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In7"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator6"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator6"
	  SrcPort		  1
	  DstBlock		  "Out4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In8"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator6"
	  DstPort		  2
	}
      }
    }
    Block {
      BlockType		      Constant
      Name		      "Constant"
      Position		      [40, 325, 70, 355]
      ShowName		      off
      Value		      "0"
    }
    Block {
      BlockType		      Constant
      Name		      "Constant1"
      Position		      [40, 365, 70, 395]
      ShowName		      off
    }
    Block {
      BlockType		      Display
      Name		      "Display1"
      Ports		      [1]
      Position		      [1165, 363, 1205, 387]
      BackgroundColor	      "cyan"
      ShowName		      off
      Decimation	      "1"
    }
    Block {
      BlockType		      Display
      Name		      "Display4"
      Ports		      [1]
      Position		      [1165, 318, 1205, 342]
      BackgroundColor	      "cyan"
      ShowName		      off
      Decimation	      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Manual Switch"
      Ports		      [2, 1]
      Position		      [90, 319, 145, 401]
      ShowName		      off
      SourceBlock	      "simulink/Signal\nRouting/Manual Switch"
      SourceType	      "Manual Switch"
      ShowPortLabels	      on
      sw		      "1"
      action		      "0"
      Port {
	PortNumber		1
	Name			"x"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "NOT 7_1"
      Ports		      [4, 4]
      Position		      [335, 325, 385, 365]
      NamePlacement	      "alternate"
      FontSize		      18
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskDisplay	      "fprintf('4x\\nNOT')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      Port {
	PortNumber		1
	Name			"__\nz1"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		2
	Name			"__\nz0"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		4
	Name			"_\nx\n"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"NOT 7_1"
	Location		[347, 737, 537, 1006]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 38, 55, 52]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 98, 55, 112]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In3"
	  Position		  [25, 163, 55, 177]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "In4"
	  Position		  [25, 223, 55, 237]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator1"
	  Ports			  [1, 1]
	  Position		  [80, 89, 110, 121]
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator2"
	  Ports			  [1, 1]
	  Position		  [80, 154, 110, 186]
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator3"
	  Ports			  [1, 1]
	  Position		  [80, 214, 110, 246]
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator7"
	  Ports			  [1, 1]
	  Position		  [80, 29, 110, 61]
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "Boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [135, 38, 165, 52]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out2"
	  Position		  [135, 98, 165, 112]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out3"
	  Position		  [135, 163, 165, 177]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out4"
	  Position		  [135, 223, 165, 237]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator7"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator1"
	  SrcPort		  1
	  DstBlock		  "Out2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In3"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator2"
	  SrcPort		  1
	  DstBlock		  "Out3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In4"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator3"
	  SrcPort		  1
	  DstBlock		  "Out4"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "RS-FF_1"
      Ports		      [2, 2]
      Position		      [725, 279, 795, 346]
      BackgroundColor	      "lightBlue"
      NamePlacement	      "alternate"
      FontSize		      18
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      Port {
	PortNumber		1
	Name			"z0"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		2
	Name			"__\nz0"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"RS-FF_1"
	Location		[478, 210, 808, 409]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "s0"
	  Position		  [15, 158, 45, 172]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "r0"
	  Position		  [15, 33, 45, 47]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 29, 120, 71]
	  ShowName		  off
	  Operator		  "OR"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator1"
	  Ports			  [2, 1]
	  Position		  [80, 134, 120, 176]
	  ShowName		  off
	  Operator		  "OR"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator2"
	  Ports			  [1, 1]
	  Position		  [145, 35, 170, 65]
	  ShowName		  off
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator3"
	  Ports			  [1, 1]
	  Position		  [145, 140, 170, 170]
	  ShowName		  off
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Memory
	  Name			  "Memory"
	  Position		  [195, 35, 225, 65]
	  ShowName		  off
	  X0			  "1"
	}
	Block {
	  BlockType		  Memory
	  Name			  "Memory1"
	  Position		  [195, 140, 225, 170]
	  ShowName		  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "q0"
	  Position		  [275, 43, 305, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "/q0"
	  Position		  [275, 148, 305, 162]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator2"
	  SrcPort		  1
	  DstBlock		  "Memory"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator3"
	  SrcPort		  1
	  DstBlock		  "Memory1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Memory1"
	  SrcPort		  1
	  Points		  [0, 0; 25, 0]
	  Branch {
	    Points		    [0, -35; -200, -40; 0, -20]
	    DstBlock		    "Logical\nOperator"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "/q0"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Memory"
	  SrcPort		  1
	  Points		  [0, 0; 25, 0]
	  Branch {
	    Points		    [0, 30; -200, 40; 0, 25]
	    DstBlock		    "Logical\nOperator1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "q0"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "s0"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "r0"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "RS-FF_2"
      Ports		      [2, 2]
      Position		      [725, 383, 795, 447]
      BackgroundColor	      "lightBlue"
      FontSize		      18
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      Port {
	PortNumber		1
	Name			"z1"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		2
	Name			"__\nz1"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"RS-FF_2"
	Location		[478, 210, 808, 409]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "s1"
	  Position		  [25, 158, 55, 172]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "r1"
	  Position		  [25, 33, 55, 47]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 29, 120, 71]
	  ShowName		  off
	  Operator		  "OR"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator1"
	  Ports			  [2, 1]
	  Position		  [80, 134, 120, 176]
	  ShowName		  off
	  Operator		  "OR"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator2"
	  Ports			  [1, 1]
	  Position		  [145, 35, 170, 65]
	  ShowName		  off
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator3"
	  Ports			  [1, 1]
	  Position		  [145, 140, 170, 170]
	  ShowName		  off
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Memory
	  Name			  "Memory"
	  Position		  [195, 35, 225, 65]
	  ShowName		  off
	  X0			  "1"
	}
	Block {
	  BlockType		  Memory
	  Name			  "Memory1"
	  Position		  [195, 140, 225, 170]
	  ShowName		  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "q1"
	  Position		  [275, 43, 305, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "/q1"
	  Position		  [275, 148, 305, 162]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator2"
	  SrcPort		  1
	  DstBlock		  "Memory"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator3"
	  SrcPort		  1
	  DstBlock		  "Memory1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Memory1"
	  SrcPort		  1
	  Points		  [0, 0; 25, 0]
	  Branch {
	    Points		    [0, -35; -200, -40; 0, -20]
	    DstBlock		    "Logical\nOperator"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "/q1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Memory"
	  SrcPort		  1
	  Points		  [0, 0; 25, 0]
	  Branch {
	    Points		    [0, 30; -200, 40; 0, 25]
	    DstBlock		    "Logical\nOperator1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "q1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "s1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "r1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "Constant"
      SrcPort		      1
      DstBlock		      "Manual Switch"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Constant1"
      SrcPort		      1
      DstBlock		      "Manual Switch"
      DstPort		      2
    }
    Line {
      Name		      "x"
      SrcBlock		      "Manual Switch"
      SrcPort		      1
      Points		      [0, 0; 65, 0]
      Branch {
	Labels			[-1, 1]
	Points			[0, 0]
	DstBlock		"NOT 7_1"
	DstPort			4
      }
      Branch {
	Points			[0, -70]
	Branch {
	  Labels		  [2, 0; -1, 1]
	  Points		  [0, -130; 690, 0; 0, 120]
	  DstBlock		  "AND\n6_2"
	  DstPort		  1
	}
	Branch {
	  Labels		  [-1, 1]
	  DstBlock		  "AND\n6_1"
	  DstPort		  1
	}
      }
      Branch {
	Points			[0, 70]
	Branch {
	  Labels		  [2, 0; -1, 1]
	  Points		  [0, 130; 690, 0; 0, -140]
	  DstBlock		  "AND\n6_2"
	  DstPort		  8
	}
	Branch {
	  Labels		  [-1, 1]
	  DstBlock		  "AND\n6_1"
	  DstPort		  8
	}
      }
    }
    Line {
      Name		      "_\nx\n"
      SrcBlock		      "NOT 7_1"
      SrcPort		      4
      Points		      [0, 0; 75, 0]
      Branch {
	Labels			[1, 0]
	Points			[0, -10]
	DstBlock		"AND\n6_1"
	DstPort			4
      }
      Branch {
	Points			[5, 0]
	DstBlock		"AND\n6_1"
	DstPort			5
      }
    }
    Line {
      Name		      "z1"
      SrcBlock		      "RS-FF_2"
      SrcPort		      1
      Points		      [0, 0; 55, 0]
      Branch {
	Labels			[1, 0]
	DstBlock		"AND\n6_2"
	DstPort			7
      }
      Branch {
	Labels			[-1, 1; 2, 1]
	Points			[0, 105; -520, 0; 0, -95]
	DstBlock		"AND\n6_1"
	DstPort			7
      }
    }
    Line {
      Name		      "z0"
      SrcBlock		      "RS-FF_1"
      SrcPort		      1
      Points		      [0, 0; 70, 0]
      Branch {
	Labels			[1, 0]
	Points			[50, 0]
	DstBlock		"AND\n6_2"
	DstPort			2
      }
      Branch {
	Labels			[2, 1; 2, 1; -1, 1]
	Points			[0, 230; -550, 0; 0, -135]
	DstBlock		"AND\n6_1"
	DstPort			6
      }
    }
    Line {
      Name		      "x.z1"
      Labels		      [-1, 1]
      SrcBlock		      "AND\n6_1"
      SrcPort		      4
      Points		      [75, 0; 0, -100]
      DstBlock		      "RS-FF_1"
      DstPort		      2
    }
    Line {
      Name		      "y1"
      Labels		      [1, 0]
      SrcBlock		      "AND\n6_2"
      SrcPort		      1
      Points		      [150, 0; 0, 45]
      DstBlock		      "Display4"
      DstPort		      1
    }
    Line {
      Name		      "y0"
      Labels		      [1, 0]
      SrcBlock		      "AND\n6_2"
      SrcPort		      4
      Points		      [150, 0; 0, -45]
      DstBlock		      "Display1"
      DstPort		      1
    }
    Line {
      Name		      "_ __\nx.z0"
      Labels		      [-1, 1]
      SrcBlock		      "AND\n6_1"
      SrcPort		      2
      Points		      [120, 0; 0, 90]
      DstBlock		      "RS-FF_2"
      DstPort		      2
    }
    Line {
      Name		      "  __\nx.z1"
      Labels		      [-1, 1]
      SrcBlock		      "AND\n6_1"
      SrcPort		      1
      DstBlock		      "RS-FF_1"
      DstPort		      1
    }
    Line {
      Name		      "_   \nx.z0"
      Labels		      [-1, 1]
      SrcBlock		      "AND\n6_1"
      SrcPort		      3
      Points		      [0, 15]
      DstBlock		      "RS-FF_2"
      DstPort		      1
    }
    Line {
      Name		      "__\nz1"
      Labels		      [3, 1; -1, 1]
      SrcBlock		      "RS-FF_2"
      SrcPort		      2
      Points		      [25, 0; 0, -225; -410, 0; 0, 105]
      DstBlock		      "AND\n6_1"
      DstPort		      2
    }
    Line {
      Name		      "__\nz0"
      Labels		      [-1, 1; 3, 1]
      SrcBlock		      "RS-FF_1"
      SrcPort		      2
      Points		      [10, 0; 0, -105; -380, 0; 0, 105]
      DstBlock		      "AND\n6_1"
      DstPort		      3
    }
    Annotation {
      Name		      "Praktikum: Digitale Grundschaltungen\nAufgabe 3"
".7: Automatenentwurf b)"
      Position		      [634, 35]
      FontSize		      18
      FontWeight	      "bold"
    }
    Annotation {
      Name		      "x"
      Position		      [151, 351]
      FontSize		      18
      FontWeight	      "bold"
    }
    Annotation {
      Name		      "  Ausdrücke f. d. Speicher- u. Ausg.gr.:  \n   "
"    _                _ __           \n  s1 = x.z0        r1 = x.z0           "
"\n         __                            \n  s0 = x.z1        r0 = x.z1      "
"     \n                                       \n  y1  = x.z0                 "
"          \n                                       \n  y0  = x.z1            "
"               \n"
      Position		      [1097, 160]
      DropShadow	      on
      TeXMode		      "on"
      FontSize		      11
    }
    Annotation {
      Name		      "y1"
      Position		      [1226, 331]
      FontSize		      18
      FontWeight	      "bold"
    }
    Annotation {
      Name		      "y0"
      Position		      [1226, 376]
      FontSize		      18
      FontWeight	      "bold"
    }
  }
}
